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Digital Design Verification
Verification of digital hardware designs at the Register-Transfer Level (RTL) usingSystem Verilog. Types of verification: formal vs. simulation-based; random vs.targeted; full-chip vs. unit-level; pre-silicon vs. post-silicon. Standardizedframeworks: Universal Verification Methodology (UVM). Assertion-basedchecking, equivalence checking.Prerequisites: EE 25 or EE 126 or graduate standing.
- School of Engineering